The present invention relates to integrated circuit isolation technology.
In integrated circuit technology, it is always necessary to separate the active regions of active devices (the "moat regions") one from another. In LSI and VLSI integrated circuits using MOS technology, this is usually performed by LOCOS (an acronym for "local oxidation of silicon"). In LOCOS, a patterned nitride is used to cover the areas which will be the moat regions, and the field oxide is then grown, by exposure to a high-temperature oxidizing ambient, in the exposed regions. However, it has long been recognized as a problem with this technology that the field oxide will not only grow vertically in the exposed regions, but will also grow laterally underneath the edges of the nitride mask. The lateral oxide encroachment (known as "bird's-beak") under the nitride is about half the field-oxide thickness, and this means that substantial real estate is wasted in this isolation technology.
A newer isolation technology, which is generally known by the acronyms SWAMI (Sidewall Masked Isolation) or MF.sup.3 R (Modified Fully Framed Fully Recessed), uses a silicon etch and sidewall nitride layer to suppress the lateral encroachment of the field oxide. That is, after the patterned first nitride layer defines the active device regions, a silicon etch is then performed where the field oxide regions will be, and a sidewall nitride is deposited (over a pad oxide) on the sidewalls of this etched recess, to avoid encroachment of the field oxide into the active device regions. This general approach has the advantage of being easily integrated in standard MOS process flows, requires no additional photomasking steps, and can reduce moat encroachment to nearly zero.
However, this process has not generally been adopted in production use, since it still has several major shortcomings.
A difficulty with process control in the prior art of sidewall-nitride isolation technologies is that, when the sidewall nitride is etched off the bottom of the silicon recess, the first nitride layer will also be thinned at the same time. This means that the final thickness of the nitride layer before the field oxidation step is somewhat uncertain, and therefore the residual moat encroachment will be more variable. (The mechanical stiffness of this nitride layer serves to reduce moat encroachment, and mechanical stiffness is very sensitive to layer thickness.)
Thus it is an object of the present invention to provide a sidewall-nitride isolation technology wherein the thickness of the first nitride layer is not reduced before the field oxidation step has been performed.
It is a further object of the present invention to provide a sidewall-nitride isolation technology wherein the thickness of the patterned nitride moat-masking layer, at the time of the channel stop implant, is precisely controlled.
It is a further object of the present invention to provide a sidewall-nitride isolation technology wherein the first patterned nitride layer is not thinned when the second nitride layer is cleared off the bottom of the etched silicon recess.
The present invention accomplishes this by performing the origional moat patterning not on a nitride/oxide stack, as is conventional, but on oxide/nitride/oxide stack. Thus, when the second nitride is conformally deposited, the stack over the moat regions is an oxide/nitride/oxide/nitride stack. When the second nitride is removed, the full thickness of the first nitride remains in place over the moat regions. Preferably the second oxide is stripped before field oxidation, so that there is no uncertainty as to the actual remaining thickness of the hard mask over the moat layers at the time of the channel stop implant. A further advantage of this additional oxide layer is that a heavier dose and energy can be used for the channel stop, without significant penetration through the hard mask.
To achieve these and other objects and advantages, the present invention provides:
A method for fabrication of integrated circuits, comprising the steps of:
providing a monocrystalline silicon substrate; PA1 covering predetermined portions of said substrate with a first patterned composite layer, comprising a silicon nitride layer and a buffer layer over said silicon nitride layer; PA1 anisotropically etching a recess in said substrate where not covered by said first patterned composite layer; PA1 depositing a sidewall masking layer to cover sidewalls of said recess, and anisotropically etching said sidewall masking layer to substantially clear the bottom of said recess; PA1 oxidizing exposed portions of silicon to form isolation oxide in said recess; PA1 removing remaining portions of said first composite layer; and PA1 forming desired active devices in portions of said substrate formerly covered by said first composite layer.